JFET(Junction Field Effect Transistor)

[vc_row][vc_column width=”2/3″][vc_column_text]

  1. What is JFET?

Figure 1. Symbols of JFET

  • A JFET is a three terminal semiconductor device in which current conduction is by one type of carrierse. by holes or electrons.
  • A JFET, or junction gate field-effect transistor, is a type of field-effect transistor. A JFET can be used as a voltage-controlled resistance or as an electronically-controlled switch.
  • A p-type JFET consists of a channel of semiconductor material containing a large amount of positive charge carriers or holes, whereas an n-type JFET consists of a channel of semiconductor material containing a large amount of negative charge carriers or holes.
  • At each end of the JFET, ohmic contacts form the source and drain. Electric charge flows through the channel between the source and drain.
  • Electric current can be impeded or switched off by applying a reverse bias voltage to a gate.

Figure 2. Construction of JFETs

  • JFET consists of a p-type or n-type silicon bar containing two pn –junctions at the side as shown in the figure above. If the bar is n-type then it is called as n-channel JFET and if the bar is p-type then it is called as p-channel JFET.
  • In the construction of n-channel JFET a narrow bar of n-type semiconductor is taken and two p-type regions are defused on the opposite sides of middle part. This forms two pn-junction diodes. These two heavily doped p-regions are internally connected and a common terminal is taken out which is known as gate terminal.
  • The ohmic contacts are at the two ends of the bar. One lead is called as the source terminal and the other is called as drain terminal. A source is a terminal through which majority carriers enter the bar and drain is the terminal through which they leave the bar.
  • Thus, FET has three terminals- gate, source and drain. For normal operation of JFET, the voltage between the gate and source is such that the gate is reverse biased.

The above figure shows the circuit for n-channel JFET with normal polarities i.e. gate is reverse biased. The circuit operation takes place as follows.

  1. When voltage VDS is applied between drain and source and if VGS = 0, then the two p-n junctions at the sides of the bar establishes depletion layers. The electrons will flow from source to drain through a channel between the depletion layers. The size of these layers determines the width of the channel and hence the current conduction through the bar.
  2. When the reverse voltage VGS is applied between the gate and source, the width of the depletion layer is increased. This reduces the width of the channel and hence current flowing through the channel reduces. If reverse voltage on the gate is decreased, the width of the depletion layer also decreases resulting in the increase width of conducting channel. Hence the current flowing through the channel increases.
  3. If the reverse voltage applied at gate terminal is increased then the depletion layers are able to touch each other due to which the channel is pinched off i.e. fully blocked due to which the current flowing through the channel becomes zero. The value of this reverse voltage VGS at which the drain current becomes zero is known as VGS (off).

From the above discussion it is clear that, the current flowing through the device is controlled by the input voltage VGS and hence this is known as voltage controlled device or Field Effect Transistor.

It may be noted that the p-channel JFET also works in the same manner except that channel current carriers will be the holes instead of electrons.


Figure 3. Output Characteristics

The output characteristics are shown in fig 3. which can be defined as the graph between the output current ID and output voltage VDS keeping input voltage VGS constant.

The different curves for different values of VGS are shown in the fig 3.

From the graph the following points can be noted. In order to explain typical shape of output characteristics, we select the curve with VGS = 0 which is subdivided in the following regions.

a. Ohmic region

If the gate is shorted with source, the maximum drain current flows through the channel which is denoted as IDSS and known as shorted gate drain current.

This region is shown as a curve OA in the figure. In this region the drain current ID increases linearly with the increase in drain to source voltage VDS obeying Ohm’s law. This linear characteristic is due to the fact that the n-type semiconductor bar acts like simple resister.

b. Curve AB ( Saturation region ) :

At point A the drain current almost becomes constant this value of VDS above which the ID becomes constant is called as pinch off voltage VP. After pinch of voltage the channel width becomes so narrow that the depletion layers almost touch each other. The drain current passed through the small passage between these layers and hence increase in drain current is very small with VDS above pinch of voltage VP. Consequently drain current ID remains constant. This region where ID is constant is known as Active region, where JFET works as a constant current source.

c. Breakdown region:

If the maximum drain voltage VDS (max) is applied to JFET then the drain current sharply increases resulting in the breakdown of JFET. Hence the region above VDS (max) is known as breakdown region. Hence the voltage applied to drain should be less than VDS (max) for safety purpose.

  1. Transfer characteristic:

The graph between the drain current ID and VGS is called as transfer characteristics of JFET. From the below graph it is clear that ID is maximum when VGS =0 and ID is zero for maximum reverse value of VGS.

Figure 4.JFET Transfer Characteristics

  1. JFET parameters:

JFET has certain parameters which determine its performance in a circuit which are as follows.

1) a.c. drain resistance (rd) :It is also called as dynamic drain resistance and defined as the ratio of change in drain to source voltage (ΔVDS) to the change in drain current (ΔID) at constant gate to source voltage VGS. rd = ΔVDS / ΔID at constant VGS.

2) Trans conductance (gm): It is defined as the ratio of change in drain current ΔID to the change in gate to source voltage ΔVGS at constant drain to source voltage VDS. gm = ΔID / ΔVGS at constant VDS

 3) Amplification factor (µ): It is defined as the ratio of change in drain to source voltage (ΔVDS) with respect to change in gate to source voltage ΔVGS keeping ID constant. µ = ΔVDS / ΔVGS at constant ID.

  • Relation between µ, gm and rd :

We know that µ = ΔVDS / ΔVGS

Dividing numerator and denominator of R.H.S by ΔID we get

µ = ( ΔVDS / ΔVGS ) * (ΔID /ΔID)

µ = (ΔVDS / ΔID) * (ΔID / ΔVGS)

µ = rd * gm[/vc_column_text][/vc_column][vc_column width=”1/3″][/vc_column][/vc_row][vc_row][vc_column width=”2/3″][vc_column_text]AUTHORS
1.Bunty B. Bommera
2.Dakshata U. Kamble[/vc_column_text][/vc_column][vc_column width=”1/3″][/vc_column][/vc_row]

Leave a Reply