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1. What is JFET?

Figure 1. Symbols of JFET

• A JFET is a three terminal semiconductor device in which current conduction is by one type of carrierse. by holes or electrons.
• A JFET, or junction gate field-effect transistor, is a type of field-effect transistor. A JFET can be used as a voltage-controlled resistance or as an electronically-controlled switch.
• A p-type JFET consists of a channel of semiconductor material containing a large amount of positive charge carriers or holes, whereas an n-type JFET consists of a channel of semiconductor material containing a large amount of negative charge carriers or holes.
• At each end of the JFET, ohmic contacts form the source and drain. Electric charge flows through the channel between the source and drain.
• Electric current can be impeded or switched off by applying a reverse bias voltage to a gate.

2. CONSTRUCTION:

Figure 2. Construction of JFETs

• JFET consists of a p-type or n-type silicon bar containing two pn –junctions at the side as shown in the figure above. If the bar is n-type then it is called as n-channel JFET and if the bar is p-type then it is called as p-channel JFET.
• In the construction of n-channel JFET a narrow bar of n-type semiconductor is taken and two p-type regions are defused on the opposite sides of middle part. This forms two pn-junction diodes. These two heavily doped p-regions are internally connected and a common terminal is taken out which is known as gate terminal.
• The ohmic contacts are at the two ends of the bar. One lead is called as the source terminal and the other is called as drain terminal. A source is a terminal through which majority carriers enter the bar and drain is the terminal through which they leave the bar.
• Thus, FET has three terminals- gate, source and drain. For normal operation of JFET, the voltage between the gate and source is such that the gate is reverse biased.

3. OPERATION:

The above figure shows the circuit for n-channel JFET with normal polarities i.e. gate is reverse biased. The circuit operation takes place as follows.

1. When voltage VDS is applied between drain and source and if V_GS = 0, then the two p-n junctions at the sides of the bar establishes depletion layers. The electrons will flow from source to drain through a channel between the depletion layers. The size of these layers determines the width of the channel and hence the current conduction through the bar.
2. When the reverse voltage V_GS is applied between the gate and source, the width of the depletion layer is increased. This reduces the width of the channel and hence current flowing through the channel reduces. If reverse voltage on the gate is decreased, the width of the depletion layer also decreases resulting in the increase width of conducting channel. Hence the current flowing through the channel increases.
3. If the reverse voltage applied at gate terminal is increased then the depletion layers are able to touch each other due to which the channel is pinched off i.e. fully blocked due to which the current flowing through the channel becomes zero. The value of this reverse voltage V_GS at which the drain current becomes zero is known as V_{GS (off)}.

From the above discussion it is clear that, the current flowing through the device is controlled by the input voltage V_GS and hence this is known as voltage controlled device or Field Effect Transistor.

It may be noted that the p-channel JFET also works in the same manner except that channel current carriers will be the holes instead of electrons.

4. OUTPUT CHARACTERISTICS OF JFET :

Figure 3. Output Characteristics

The output characteristics are shown in fig 3. which can be defined as the graph between the output current I_D and output voltage V_DS keeping input voltage V_GS constant.

The different curves for different values of VGS are shown in the fig 3.

From the graph the following points can be noted. In order to explain typical shape of output characteristics, we select the curve with V_GS = 0 which is subdivided in the following regions.

a. Ohmic region

If the gate is shorted with source, the maximum drain current flows through the channel which is denoted as I_DSS and known as shorted gate drain current.

This region is shown as a curve OA in the figure. In this region the drain current I_D increases linearly with the increase in drain to source voltage V_DS obeying Ohm’s law. This linear characteristic is due to the fact that the n-type semiconductor bar acts like simple resister.

b. Curve AB ( Saturation region ) :

At point A the drain current almost becomes constant this value of V_DS above which the I_D becomes constant is called as pinch off voltage V_P. After pinch of voltage the channel width becomes so narrow that the depletion layers almost touch each other. The drain current passed through the small passage between these layers and hence increase in drain current is very small with V_DS above pinch of voltage V_P. Consequently drain current I_D remains constant. This region where I_D is constant is known as Active region, where JFET works as a constant current source.

c. Breakdown region:

If the maximum drain voltage V_{DS (max)} is applied to JFET then the drain current sharply increases resulting in the breakdown of JFET. Hence the region above V_{DS (max)} is known as breakdown region. Hence the voltage applied to drain should be less than V_{DS (max)} for safety purpose.

5. Transfer characteristic:

The graph between the drain current I_D and V_GS is called as transfer characteristics of JFET. From the below graph it is clear that I_D is maximum when V_GS =0 and I_D is zero for maximum reverse value of V_GS.

Figure 4.JFET Transfer Characteristics

6. JFET parameters:

JFET has certain parameters which determine its performance in a circuit which are as follows.

1) a.c. drain resistance (rd) :It is also called as dynamic drain resistance and defined as the ratio of change in drain to source voltage (ΔV_DS) to the change in drain current (ΔI_D) at constant gate to source voltage V_GS. r_d = ΔV_DS / ΔI_D at constant V_GS.

2) Trans conductance (gm): It is defined as the ratio of change in drain current ΔI_D to the change in gate to source voltage ΔV_GS at constant drain to source voltage V_DS. g_m = ΔI_D / ΔV_GS at constant V_DS

 3) Amplification factor (µ): It is defined as the ratio of change in drain to source voltage (ΔV_DS) with respect to change in gate to source voltage ΔV_GS keeping I_D constant. µ = ΔV_DS / ΔV_GS at constant I_D.

• Relation between µ, gm and rd :

We know that µ = ΔV_DS / ΔV_GS

Dividing numerator and denominator of R.H.S by ΔI_D we get

µ = ( ΔV_DS / ΔV_GS ) * (ΔI_D /ΔI_D)

µ = (ΔV_DS / ΔI_D) * (ΔI_D / ΔV_GS)

µ = r_d * g_m[/vc_column_text][/vc_column][vc_column width=”1/3″][/vc_column][/vc_row][vc_row][vc_column width=”2/3″][vc_column_text]AUTHORS
1.Bunty B. Bommera
2.Dakshata U. Kamble[/vc_column_text][/vc_column][vc_column width=”1/3″][/vc_column][/vc_row]